1. Field
The present description relates to exposure masks for photolithography and, in particular, to a deformable mask holder to provide improved flatness for the mask.
2. Related Art
To increase the number of transistors, diodes, resistors, capacitors, other circuit elements, or mechanical devices on an integrated circuit or micromechanical chip, these devices are placed closer and closer together. This requires that each device be made smaller. Current state-of-the art manufacturing technologies use laser light with a wavelength of 193 nm for photolithography. These are referred to as Deep Ultraviolet (DUV) systems. These systems are being continuously improved and are projected to be able to produce features as small as 20 nm. However, at some point, it is anticipated that a different technology must be applied to continue reducing the size of features using photolithography.
One obstacle to producing still smaller features by photolithography is the wavelength of the light being used. The next step that has been proposed is to use light of 13.4 nm, or other wavelengths in the range of 4 nm-30 nm, referred to as Extreme Ultraviolet (EUV) light. Depending on the rest of the system and process parameters, this light may allow features to be created that are less than 20 nm across and probably as small as 10 nm or less across.
The smaller size of the printed features is a result of the improvement in resolution. The resolution of a photolithography system is proportional to the wavelength of the light divided by the numerical aperture of the illumination system's projection optics. As a result, the resolution can be improved by either decreasing the wavelength of the light used, or by increasing the numerical aperture (NA) of the photolithography projection optics, or both.
As the wavelength of the illumination light is decreased, the lithography process becomes more difficult and more expensive. All known materials absorb EUV light. As a result, the projection optics and the masks used to pattern a substrate using EUV light must be reflective. The shorter wavelength and smaller size of the printed features also increase the requirements for accuracy in all other parts of the lithography system. Typically, the accuracy requirements increase at least proportionally to the reduction in the size of the printed features.
One difficulty in EUV lithography is to ensure that the reflective surface of the EUV mask, also referred to as a reticle, is flat. The reflective surface of the EUV mask may be uneven due to general bowing from weight or from film stresses. It may be uneven due to polishing of the mask substrate and due to bulges created by particles that are trapped on the surfaces that support the mask blank. Variations in the flatness of the reflecting surface of the mask result in positional errors in the projected image on the wafers that are being patterned.
The positional errors are caused, in part, by using a reflective mask. In order to use a reflective mask, the light must hit the mask at an angle in one direction so that it is reflected at an angle in the opposite direction. Proposed angles are about 6 degrees from a normal to the mask surface. For imaging small features using reflective EUV optics, the acceptable placement errors of the features on the silicon wafer (typically less than about 10% of the minimum feature size) requires that the reflecting mask surfaces be flat to within about 50 nm while imaging.
So far, a sufficiently flat reflective EUV mask blank has not been made. In addition, the mask blanks that have been demonstrated become even less flat while the blank is supported in an EUV lithography apparatus, such as a scanner, using for example, an electrostatic chuck. The cost of EUV lithography becomes significantly higher if exceptionally flat EUV blanks are required. In high volume manufacturing, maintaining the mask support surfaces free of particles (which would otherwise distort the front surface flatness) is also a major concern. If the mask stage in EUV wafer exposure tools must be cleaned often, then costs will also be increased because the tool, for example the electrostatic chuck, cannot be used to expose wafers while it is being cleaned.
The current approach being developed for EUV lithography is to obtain mask blanks whose surfaces are flatter than is required so that when these blanks are held using an electrostatic chuck in the EUV scanners, the front reflective surface will meet the flatness specification. These very flat mask blanks are very expensive and so far there are no electrostatic chucks available that can keep the mask blanks flat enough. As semiconductor device dimensions decrease even further, the requirements for flatness become even greater, so that the flatness of the mask becomes a limitation on how many transistors can be formed on a chip.